MPC8379ECVRALGA datasheet(74/114 Pages) FREESCALE

74 / 114 page

MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

output driver features a 50-

Ω termination resistor. It also assumes that the LVDS transmitter establishes its

own common mode level without relying on the receiver or other external component.

Figure 54. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 55 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

device SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 55 assumes

that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL outputs

prior to AC-coupling. Its value could be ranged from 140

Ω to 240 Ω depending on clock driver vendor’s

requirement. R2 is used together with the SerDes reference clock receiver’s 50

Ω termination resistor to

attenuate the LVPECL output’s differential peak level such that it meets the device SerDes reference

clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For

example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input

amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Please consult

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8379E

MPC8379ECVRALGA Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc