CPC7594MATR datasheet(15/20 Pages) CLARE

15 / 20 page

CPC7594

R03

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Pull TSD to a logic low to end the ringing state.

This opens the ringing return switch (SW3) and

prevents any other switches from closing.

Keep TSD low for at least one-half the duration of

the ringing cycle period to allow sufficient time for

a zero crossing current event to occur and for the

circuit to enter the break-before-make state.

During the TSD low period, set the INRINGING and

INTEST inputs to the talk state (0, 0).

Release TSD, allowing the internal pull-up to

activate the break switches.

When using TSD as an input, the two recommended

states are “0” which overrides the logic input pins and

forces an all off state and “Z” which allows normal

switch control via the logic input pins. This requires the

use of an open-collector or open-drain type buffer.

Forcing TSD to a logic high prevents the user from

detecting a thermal shutdown condition and is

therefore not recommended.

Alternate Break-Before-Make Ringing to Talk Transition Logic Sequence

2.4 Data Latch

The CPC7594 has an integrated transparent data

latch. The latch enable operation is controlled by TTL

logic input levels at the LATCH pin. Data input to the

latch is via the input pins INRINGING and INTEST while

the output of the data latch are internal nodes used for

state control. When the LATCH enable control pin is at

a logic 0 the data latch is transparent and the input

control signals flow directly through the data latch to

the state control circuitry. A change in input will be

reflected by a change in the switch state.

Whenever the LATCH enable control pin is at logic 1,

the data latch is active and data is locked. Subsequent

changes to the input controls INRINGING and INTEST

will not result in a change to the control logic or affect

the existing switch state.

The switches will remain in the state they were in

when the LATCH changes from logic 0 to logic 1 and

will not respond to changes in input as long as the

LATCH is at logic 1. However, neither the TSD input

nor the TSD output control functions are affected by

the latch function. Since internal thermal shutdown

control and external “All-off” control is not affected by

the state of the LATCH enable input, TSD will override

state control.

2.5 TSD Pin Description

The TSD pin is a bi-directional I/O structure with an

internal pull-up current source having a nominal value

of 16

μA biased from V

DD.

As an output, this pin indicates the status of the

thermal shutdown circuitry. Typically, during normal

operation, this pin will be pulled up to VDD but under

fault conditions that create excess thermal loading the

CPC7594 will enter thermal shutdown and a logic low

will be output.

State

INRINGING

INTEST LATCH

TSD

Timing

Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing

Off

All-Off

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero

current to turn off.

Off

Break-

Before-

Make

SW4 has opened

Off

Talk

Close Break Switches

Off

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