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ICS8524 Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS8524 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 17 page ![]() 8524AY www.icst.com/products/hiperclocks.html REV. B AUGUST 1, 2007 8 ICS8524 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT R2 1K V DD CLK_IN + - R1 1K C1 0.1uF V_REF WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. |
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