ATmega128 datasheet(96/386 Pages) ATMEL

96 / 386 page

2467S–AVR–07/09

ATmega128

Figure 36. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0 buffer Register, and if double buffering is disabled

the CPU will access the OCR0 directly.

Force Output

Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0) bit. Forcing compare match will not set the

OCF0 flag or reload/clear the timer, but the OC0 pin will be updated as if a real compare match

had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled).

Compare Match

Blocking by TCNT0

Write

All CPU write operations to the TCNT0 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized

to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output

Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the output compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0 value, the compare match will be missed, resulting in incorrect waveform gen-

eration. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register for the port

pin to output. The easiest way of setting the OC0 value is to use the force output compare

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCxy

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

ATmega128 Datasheet(PDF) 96 Page - ATMEL Corporation

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