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ATmega128 Datasheet(PDF) 145 Page - ATMEL Corporation |
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ATmega128 Datasheet(HTML) 145 Page - ATMEL Corporation |
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145 / 386 page ![]() 145 2467S–AVR–07/09 ATmega128 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_I/O/2.5. An external clock source can not be prescaled. Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3 Note: The synchronization logic on the input pins ( T3/T2/T1) is shown in Figure 59. Special Function IO Register – SFIOR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during con- figuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a reset of this prescaler will affect all three timers. PSR321 Clear clk T2 TIMER/COUNTER2 CLOCK SOURCE 0 CS20 CS21 CS22 T2 clk T1 TIMER/COUNTER1 CLOCK SOURCE 0 CS10 CS11 CS12 T1 clk T3 TIMER/COUNTER3 CLOCK SOURCE 0 CS30 CS31 CS32 T3 10-BIT T/C PRESCALER CK Bit 7 6 5 4 3 2 1 0 TSM – – – ACME PUD PSR0 PSR321 SFIOR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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