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ATmega128 Datasheet(PDF) 371 Page - ATMEL Corporation |
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ATmega128 Datasheet(HTML) 371 Page - ATMEL Corporation |
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371 / 386 page ![]() 371 2467S–AVR–07/09 ATmega128 Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. F to M • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • Stabilizing time needed when changing OSCCAL Register • IDCODE masks data from TDI input • Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising V CC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 3. Stabilizing time needed when changing XDIV Register After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8 instructions after the change should be NOP instructions. To ensure this, follow this procedure: 1.Clear the I bit in the SREG Register. 2.Set the new pre-scaling factor in XDIV register. 3.Execute 8 NOP instructions 4.Set the I bit in SREG This will ensure that all subsequent instructions will execute correctly. Assembly Code Example: CLI ; clear global interrupt enable OUT XDIV, temp ; set new prescale value NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation |
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