ATmega165 datasheet(182/336 Pages) ATMEL

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182

ATmega165/V

2573G–AVR–07/09

(transparent) during the first half of a serial clock cycle when an external clock source is

selected (USICS1 = 1), and constantly open when an internal clock source is used

(USICS1 = 0). The output will be changed immediately when a new MSB written as long

as the latch is open. The latch ensures that data input is sampled and data output is

changed on opposite clock edges.

Note that the corresponding Data Direction Register to the pin must be set to one for

enabling data output from the Shift Register.

USI Status Register – USISR

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition

is detected. When output disable mode or Three-wire mode is selected, the flag is set

when the 4-bit counter is incremented.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the

Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one

to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-

wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to

0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and

the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written

to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-

wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is

detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt

Flag. This signal is useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.

The flag is only valid when Two-wire mode is used. This signal is useful when imple-

menting Two-wire bus master arbitration.

• Bits 3..0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be

read or written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external

clock edge detector, by a Timer/Counter0 Compare Match, or by software using USI-

Bit

210

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

Read/Write

R/W

Initial Value

ATmega165 Datasheet(PDF) 182 Page - ATMEL Corporation

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