AT89LP6440 datasheet(101/194 Pages) ATMEL

101 / 194 page

101

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Notes:1. In these modes MOSI is active only during transfers. MOSI will be pulled high between trans-

fers to allow other masters to control the line.

2. In Push-Pull mode MOSI is active only during transfers, otherwise it is tristated to prevent line

contention. A weak external pull-up may be required to prevent MOSI from floating.

Table 17-1.

SPI Pin Configuration and Behavior when SPE = 1

Mode

Master (MSTR = 1)

Slave (MSTR = 0)

SCK

Quasi-bidirectionalOutputInput (Internal Pull-up)

Push-Pull OutputOutputInput (Tristate)

Input-Only

No output (Tristated)

Input (Tristate)

Open-Drain OutputOutput

Input (External Pull-up)

MOSI

Quasi-bidirectionalOutput(1)

Input (Internal Pull-up)

Push-Pull OutputOutput(2)

Input (Tristate)

Input-Only

No output (Tristated)

Input (Tristate)

Open-Drain OutputOutput(1)

Input (External Pull-up)

MISO

Quasi-bidirectionalInput (Internal Pull-up)

Output (SS = 0)

Internal Pull-up (SS = 1 or DISSO = 1)

Push-Pull OutputInput (Tristate)

Output (SS = 0)

Tristated (SS = 1 or DISSO = 1)

Input-Only

Input (Tristate)

No output (Tristated)

Open-Drain OutputInput (External Pull-up)

Output (SS = 0)

External Pull-up (SS = 1 or DISSO = 1)

Table 17-2.

SPCR – SPI Control Register

SPCR Address = E9H

Reset Value = 0000 0000B

Not Bit Addressable

TSCK

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

765432

Symbol

Function

TSCK

SCK Clock Mode. When TSCK = 0, the SCK baud rate is based on the system clock, divided by the SPR1-0 ratio.When

TSCK = 1, the SCK baud rate is based on the Timer 1 overflow rate, divided by the SPR

1-0 ratio.

SPE

SPI enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7.

SPI = 0 disables the SPI channel.

DORD

Data order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

MSTR

Master/slave select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.

CPOL

Clock polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

transmitting. Please refer to figure on SPI clock phase and polarity control.

CPHA

Clock phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

slave. Please refer to figure on SPI clock phase and polarity control.

AT89LP6440 Datasheet(PDF) 101 Page - ATMEL Corporation

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