AT89LP6440 datasheet(112/194 Pages) ATMEL

112 / 194 page

112

3706A–MICRO–9/09

AT89LP6440 - Preliminary

18.5

Using the TWI

The AT89LP TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events,

like reception of a byte or transmission of a START condition. Because the TWI is interrupt-

based, the application software is free to carry on other operations during a TWI byte transfer.

Note that the TWI Interrupt Enable (TWE) bit in IE2 together with the Global Interrupt Enable bit

in EA allow the application to decide whether or not assertion of the TWIF flag should generate

an interrupt request. If the TWE bit is cleared, the application must poll the TWIF flag in order to

detect actions on the TWI bus.

When the TWIF flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR registers.

Figure 18-10 is a simple example of how the application can interface to the TWI hardware. In

this example, a Master wishes to transmit a single data byte to a Slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Table 18-4.

TWDR – Two-Wire Data Register

TWDR Address = ADH

Reset Value = 1111 1111B

Not Bit Addressable

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

Bit

76543

210

Symbol

Function

TWD

7-0

Two-wire Interface Data. Writes to TWDR queue the next address or data byte for transmission. Reads from TWDR

return the last address or data byte present on the bus. Writes/reads to/from TWDR must occur only while TWIF is set.

Writes to TWDR while TWIF = 0 are ignored. Reads from TWDR while TWIF = 0 may return random data.

Table 18-5.

TWBR – Two-Wire Bit Rate Register

TWBR Address = AEH

Reset Value = 0000 0000B

Not Bit Addressable

TWB7

TWB6

TWB5

TWB4

TWB3

TWB2

TWB1

TWB0

Bit

76543

210

Symbol

Function

TWB7-0

Two-wire Interface Serial Bit Rate. TWBR is an 8-bit down counter that selects the division factor (

÷1–256) for the bit rate

generator. The bit rate generator is a frequency divider which generates the SCL clock frequency from the system clock

in Master mode.

AT89LP6440 Datasheet(PDF) 112 Page - ATMEL Corporation

AT89LP6440 Datasheet(HTML) 112 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL