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AT89LP6440 Datasheet(PDF) 128 Page - ATMEL Corporation

Part # AT89LP6440
Description  8-bit Microcontroller with 64K Bytes In-System Programmable Flash
PDF  194 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89LP6440 Datasheet(HTML) 128 Page - ATMEL Corporation

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3706A–MICRO–9/09
AT89LP6440 - Preliminary
Figure 19-2. Equivalent Analog Input Model
19.2
Internal Reference Voltage
The negative input terminal of each comparator may be connected to an internal voltage refer-
ence by changing the RFB
1-0 or RFA1-0 bits in AREF. The internal reference voltage, VAREF, is
set to 1.25 V ±5%. The voltage reference also provides two additional voltage levels approxi-
mately 125 mV above and below V
AREF. These levels may be used to configure the comparators
as an internally referenced window comparator with up to four input channels. Changing the ref-
erence input must follow the same routine used for changing the positive input as described in
“Analog Input Muxes” above.
19.3
Comparator Interrupt Debouncing
The comparator output is normally sampled every clock cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if
applying slow moving analog inputs. Three debouncing modes are provided to filter out this
noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-
late its sampling time when CxC
1-0 = 00B. When a relevant transition occurs, the comparator
waits until two Timer 1 overflows have occurred before resampling the output. If the new sample
agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be
tuned by adjusting the time-out period of Timer 1. Because Timer 1 is free running, the
debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out
period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out
periods later. See Figure 19-3. When the comparator clock is provided by one of the timer over-
flows, i.e. CxC
1-0 != 00B, any change in the comparator output must be valid after 4 samples to
be accepted as an edge event.
Figure 19-3. Negative Edge with Debouncing Example
AINn
CCMP <
0.3 pF
RIN =
10 k
Ω
CPIN =
10 pF
RMUX =
10 k
Ω
Comparator Out
Timer 1 Overflow
CFx
Start
Start
Compare
(rejected)
Compare
(accepted)



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