AT697F datasheet(100/155 Pages) ATMEL

100 / 155 page

Bit Number

Mnemonic

Description

ec1

External Clock

if set, the UART scaler will be clocked by PIO[3]

lb1

Loop back

If set, loop back mode will be enabled.

fl1

Flow control

If set, enables flow control using CTS/RTS.

pe1

Parity enable

If set, enables parity generation and checking.

ps1

Parity select

Selects parity polarity

‘0’ = even parity

‘1’ = odd parity

ti1

Transmitter interrupt enable

If set, enables generation of transmitter interrupt.

ri1

Receiver interrupt enable

If set, enables generation of receiver interrupt.

te1

Transmitter enable

If set, enables the transmitter.

re1

Receiver enable

If set, enables the receiver.

Table 71. UART 1 Scaler Register - UASCA1

Address = 0x8000007C

reserved

scaler value1 [11:0]

r/w

xxxx xxxx xxxx xxxx xxxx

xxxx xxxx xxxx

Table 72. UART 2 Data Register - UAD2

Address = 0x80000080

reserved

rtd2 [7:0]

r/w

xxxx xxxx xxxx xxxx xxxx xxxx

xxxx xxxx

Bit Number

Mnemonic

Description

7..0

rtd2[7:0]

Received or Transmitted Data of UART2

100

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

rtd1 field has 2 meanings :

A write access enables the sending of the written 8-bit data on UART 2.

A read access provides the received 8-bit data on UART2.

AT697F Datasheet(PDF) 100 Page - ATMEL Corporation

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