ATmega16U4 datasheet(216/408 Pages) ATMEL

216 / 408 page

216

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

19.3

SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which

are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are

shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCKn

signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-

ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.

19.4

Frame Formats

A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM

mode has two valid frame formats:

• 8-bit data with MSB first

• 8-bit data with LSB first

A frame starts with the least or most significant data bit. Then the next data bits, up to a total of

eight, are succeeding, ending with the most or least significant bit accordingly. When a complete

frame is transmitted, a new frame can directly follow it, or the communication line can be set to

an idle (high) state.

Table 19-2.

UCPOLn and UCPHAn Functionality-

UCPOLn

UCPHAn

SPI Mode

Leading Edge

Trailing Edge

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

UCPOL=0

UCPOL=1

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