ATmega16U4 datasheet(274/408 Pages) ATMEL

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274

7766D–AVR–01/09

ATmega16U4/ATmega32U4

switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accor-

dance with the status of the new bank.

RXOUTI shall always be cleared before clearing FIFOCON.

The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can

read data from the bank, and cleared by hardware when the bank is empty.

22.13.2

Detailed description

22.13.2.1

The data are read by the CPU, following the next flow:

• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled

(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending

on the software architecture,

• The CPU acknowledges the interrupt by clearing RXOUTI,

• The CPU can read the number of byte (N) in the current bank (N=BYCT),

• The CPU can read the data from the current bank (“N” read of UEDATX),

• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:

– after “N” read of UEDATX,

– as soon as RWAL is cleared by hardware.

If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is

being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already

ready and RXOUTI is set immediately.

OUT

DATA

(to bank 0)

ACK

RXOUTI

FIFOCON

OUT

DATA

(to bank 0)

ACK

Example with 1 OUT data bank

read data from CPU

BANK 0

OUT

DATA

(to bank 0)

ACK

RXOUTI

FIFOCON

OUT

DATA

(to bank 1)

ACK

Example with 2 OUT data banks

read data from CPU

BANK 0

read data from CPU

BANK 0

read data from CPU

BANK 1

NAK

ATmega16U4 Datasheet(PDF) 274 Page - ATMEL Corporation

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