ATmega16U4 datasheet(363/408 Pages) ATMEL

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363

7766D–AVR–01/09

ATmega16U4/ATmega32U4

28.8

Serial Programming Pin Mapping

Figure 28-10. Serial Programming and Verify

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Notes:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

28.8.1

Serial Programming Algorithm

When writing serial data to the ATmega16U4/ATmega32U4, data is clocked on the rising edge

of SCK.

When reading data from the ATmega16U4/ATmega32U4, data is clocked on the falling edge of

SCK. See Figure 28-11 for timing details.

To program and verify the ATmega16U4/ATmega32U4 in the serial programming mode, the fol-

lowing sequence is recommended (See four byte instruction formats in Table 28-16):

Table 28-14. Pin Mapping Serial Programming

Symbol

Pins

(TQFP-64)

I/O

Description

PDI

PB2

Serial Data in

PDO

PB3

Serial Data out

SCK

PB1

Serial Clock

VCC

GND

XTAL1

SCK

PDO

PDI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

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