ATmega16U4 datasheet(384/408 Pages) ATMEL

384 / 408 page

384

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Notes:

1. In ATmega16U4/ATmega32U4, this parameter is characterized and not 100% tested.

2. Required only for fSCL > 100 kHz.

3. Cb = capacitance of one bus line in pF.

4. f

CK = CPU clock frequency

5. This requirement applies to all ATmega16U4/ATmega32U4 2-wire Serial Interface operation. Other devices connected to the

2-wire Serial Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f

SCL - 2/fCK), thus fCK must

be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega16U4/ATmega32U4 2-wire Serial Interface is (1/f

SCL - 2/fCK), thus the low

time requirement will not be strictly met for f

SCL > 308 kHz when fCK = 8 MHz. Still, ATmega16U4/ATmega32U4 devices con-

nected to the bus may communicate at full speed (400 kHz) with other ATmega16U4/ATmega32U4 devices, as well as any

other device with a proper t

LOW acceptance margin.

Figure 29-3. 2-wire Serial Bus Timing

tHIGH

High period of the SCL clock

SCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

SCL > 100 kHz

0.6

–

µs

HD;DAT

Data hold time

fSCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

SCL ≤ 100 kHz

250

–

fSCL > 100 kHz

100

–

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

BUF

Bus free time between a STOP and START

condition

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

1.3

–

µs

Table 29-2.

2-wire Serial Bus Requirements (Continued)

Symbol

Parameter

Condition

Min

Max

Units

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

ATmega16U4 Datasheet(PDF) 384 Page - ATMEL Corporation

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