ATmega16M1 datasheet(138/365 Pages) ATMEL

138 / 365 page

138

7647F–AVR–04/09

ATmega16/32/64/M1/C1

The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is

able to count up to a top value determined by the contents of POCR_RB register and then

according to the selected running mode, count down or reset to zero for another cycle.

As can be seen from the block diagram Figure 14-1, the PSC is composed of 3 modules.

Each of the 3 PSC modules can be seen as two symetrical entities. One entity named part A

which generates the output PSCOUTnA and the second one named part B which generates the

PSCOUTnB output.

Each module has its own PSC Input circuitry which manages the corresponding input.

14.5

Functional Description

14.5.1

Generation of Control Waveforms

In general, the drive of a 3 phase motor requires the generation of 6 PWM signals. The duty

cycle of these signals must be independently controlled to adjust the speed or torque of the

motor or to produce the wanted waveform on the 3 voltage lines (trapezoidal, sinusoidal...)

In case of cross conduction or overtemperature, having inputs which can immediately disable

the waveform generator’s outputs is desirable.

These considerations are common for many systems which require PWM signals to drive power

systems such as lighting, DC/DC converters...

14.5.2

Waveform Cycles

Each of the 3 modules has 2 waveform generators which jointly compose the output signal.

The first part of the waveform is relative to part A or PSCOUTnA output. This waveform corre-

sponds to sub-cycle A in the following figure.

The second part of the waveform is relative to part B or PSCOUTnB output. This waveform cor-

responds to sub-cycle B in the following figure.

The complete waveform is terminated at the end of the sub-cycle B, whereupon any changes to

the settings of the waveform generator registers will be implemented, for the next cycle.

The PSC can be configured in one of two modes (1Ramp Mode or Centered Mode). This config-

uration will affect the operation of all the waveform generators.

Figure 14-2. Cycle Presentation in One Ramp Mode

Sub-Cycle A

Sub-Cycle B

One PSC Cycle

UPDATE

PSC Counter Value

ATmega16M1 Datasheet(PDF) 138 Page - ATMEL Corporation