ATmega328P datasheet(141/345 Pages) ATMEL

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7810A–AVR–11/09

ATmega328P [Preliminary]

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform

Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2x state before the out-

put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 150.

17.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the

OC2x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 17-5 on page 151. For fast PWM mode, refer to Table 17-6 on

page 151, and for phase correct PWM refer to Table 17-7 on page 152.

A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2x strobe bits.

17.7

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output

mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See “Compare Match Output Unit” on page 140.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 146.

17.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

ATmega328P Datasheet(PDF) 141 Page - ATMEL Corporation

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