ATmega328P datasheet(143/345 Pages) ATMEL

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7810A–AVR–11/09

ATmega328P [Preliminary]

17.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In

non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare

match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2x and TCNT2.

Figure 17-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.

Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,

and OCR2A when MGM2:0 = 7. (See Table 17-3 on page 150). The actual OC2x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by setting (or clearing) the OC2x Register at the compare match between

OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the

counter is cleared (changes from TOP to BOTTOM).

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

ATmega328P Datasheet(PDF) 143 Page - ATMEL Corporation