ATmega328P datasheet(146/345 Pages) ATMEL

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7810A–AVR–11/09

ATmega328P [Preliminary]

• OCR2A changes its value from MAX, like in Figure 17-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting compare match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an

up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the way

up.

17.8

Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk

T2)

is therefore shown as a clock enable signal. In asynchronous mode, clk

I/O should be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 17-8. Timer/Counter Timing Diagram, no Prescaling

Figure 17-9 shows the same timing data, but with the prescaler enabled.

Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

Figure 17-10 shows the setting of OCF2A in all modes except CTC mode.

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

ATmega328P Datasheet(PDF) 146 Page - ATMEL Corporation

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