ATmega328P datasheet(149/345 Pages) ATMEL

149 / 345 page

149

7810A–AVR–11/09

ATmega328P [Preliminary]

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous

timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least

one before the processor can read the timer value causing the setting of the Interrupt Flag. The

Output Compare pin is changed on the timer clock and is not synchronized to the processor

clock.

17.10 Timer/Counter Prescaler

Figure 17-12. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clk

T2S. clkT2S is by default connected to the main

system I/O clock clk

IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal.

For Timer/Counter2, the possible prescaled selections are: clk

T2S/8, clkT2S/32, clkT2S/64,

clk

T2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clk

I/O

clk

T2S

TOSC1

AS2

CS20

CS21

CS22

PSRASY

Clear

clk

ATmega328P Datasheet(PDF) 149 Page - ATMEL Corporation