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ATmega328P Datasheet(PDF) 259 Page - ATMEL Corporation |
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ATmega328P Datasheet(HTML) 259 Page - ATMEL Corporation |
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259 / 345 page  259 7810A–AVR–11/09 ATmega328P [Preliminary] 23.9.3 ADCL and ADCH – The ADC Data Register 23.9.3.1 ADLAR = 0 23.9.3.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 254. 23.9.4 ADCSRB – ADC Control and Status Register B • Bit 7, 5:3 – Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bist must be written to zero when ADCSRB is written. Bit 151413 121110 9 8 (0x79) – –––– – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6543 210 Read/Write RRR RRR RR RRR RRR RR Initial Value 0 0000 000 0 0000 000 Bit 151413121110 9 8 (0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH (0x78) ADC1 ADC0 – – – – – – ADCL 7 654 321 0 Read/Write RR RRR RRR RR RRR RRR Initial Value 0 0 0 0 0 0 0 0 0 000 000 0 Bit 7 6543 210 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0000 000 |
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