ATtiny13A datasheet(106/174 Pages) ATMEL

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8126D–AVR–11/09

ATtiny13A

17.6 Serial Programming

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). See Figure 17-1.

Figure 17-1. Serial Programming and Verify

Note:

If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.

After RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase operations can be executed.

Note:

In Table 17-7 above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins

dedicated for the internal SPI interface.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

Table 17-7.

Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB0

Serial Data in

MISO

PB1

Serial Data out

SCK

PB2

Serial Clock

VCC

GND

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

PB0

PB1

PB2

PB5

ATtiny13A Datasheet(PDF) 106 Page - ATMEL Corporation

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