ATtiny13A datasheet(56/174 Pages) ATMEL

56 / 174 page

8126D–AVR–11/09

ATtiny13A

Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 54.

Note:

1. 1 when the fuse is “0” (Programmed).

Table 10-3.

Port B Pins Alternate Functions

Port Pin

Alternate Function

PB5

RESET: Reset Pin

dW:

debugWIRE I/O

ADC0: ADC Input Channel 0

PCINT5: Pin Change Interrupt, Source 5

PB4

ADC2: ADC Input Channel 2

PCINT4: Pin Change Interrupt 0, Source 4

PB3

CLKI:

External Clock Input

ADC3: ADC Input Channel 3

PCINT3: Pin Change Interrupt 0, Source 3

PB2

SCK:

Serial Clock Input

ADC1: ADC Input Channel 1

T0:

Timer/Counter0 Clock Source.

PCINT2: Pin Change Interrupt 0, Source 2

PB1

MISO:

SPI Master Data Input / Slave Data Output

AIN1:

Analog Comparator, Negative Input

OC0B: Timer/Counter0 Compare Match B Output

INT0:

External Interrupt 0 Input

PCINT1:Pin Change Interrupt 0, Source 1

PB0

MOSI:: SPI Master Data Output / Slave Data Input

AIN0:

Analog Comparator, Positive Input

OC0A: Timer/Counter0 Compare Match A output

PCINT0: Pin Change Interrupt 0, Source 0

Table 10-4.

Overriding Signals for Alternate Functions in PB5:PB3

Signal

PB5/RESET/ADC0/PCINT5

PB4/ADC2/PCINT4

PB3/ADC3/CLKI/PCINT3

PUOE

RSTDISBL(1) • DWEN(1)

PUOV

100

DDOE

RSTDISBL(1) • DWEN(1)

DDOV

debugWire Transmit

PVOE

PVOV

PTOE

000

DIEOE

RSTDISBL(1) + (PCINT5 •

PCIE + ADC0D)

PCINT4 • PCIE + ADC2D

PCINT3 • PCIE + ADC3D

DIEOV

ADC0D

ADC2D

ADC3D

PCINT5 Input

PCINT4 Input

PCINT3 Input

AIO

RESET Input, ADC0 Input

ADC2 Input

ADC3 Input

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