ATmega16A datasheet(259/352 Pages) ATMEL

259 / 352 page

259

8154B–AVR–07/09

ATmega16A

as described in “Interrupts” on page 44, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on

page 260 for an example.

25.8.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and

execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the

Boot Lock bits that may prevent the Application and Boot Loader section from any software

update by the MCU.

See Table 25-2 and Table 25-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It

is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-

gramming the Lock bits the entire Flash can be read during the operation.

25.8.8

EEPROM Write Prevents Writing to SPMCR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCR Register.

25.8.9

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction

is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the

value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits

will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the

Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and

SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLB-

SET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded

in the destination register as shown below. Refer to Table 26-4 on page 266 for a detailed

description and mapping of the Fuse Low bits.

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,

Bit

543210

BLB12

BLB11

BLB02

BLB01

Bit

543210

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

3210

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

ATmega16A Datasheet(PDF) 259 Page - ATMEL Corporation

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