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ATmega32A Datasheet(PDF) 147 Page - ATMEL Corporation |
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ATmega32A Datasheet(HTML) 147 Page - ATMEL Corporation |
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147 / 352 page ![]() 147 8155B–AVR–07/09 ATmega32A 19. USART 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 19.2 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. A simplified block diagram of the USART transmitter is shown in Figure 19-1. CPU accessible I/O Registers and I/O pins are shown in bold. |
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