ATmega32A datasheet(149/352 Pages) ATMEL

149 / 352 page

149

8155B–AVR–07/09

ATmega32A

19.2.1

AVR USART vs. AVR UART – Compatibility

The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers

• Baud Rate Generation

• Transmitter Operation

• Transmit Buffer Functionality

• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in some

special cases:

• A second Buffer Register has been added. The two Buffer Registers operate as a circular

FIFO buffer. Therefore the UDR must only be read once for each incoming data! More

important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are

buffered with the data in the receive buffer. Therefore the status bits must always be read

before the UDR Register is read. Otherwise the error status will be lost since the buffer state

is lost.

• The receiver Shift Register can now act as a third buffer level. This is done by allowing the

received data to remain in the serial Shift Register (see Figure 19-1) if the Buffer Registers

are full, until a new start bit is detected. The USART is therefore more resistant to Data

OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register location:

• CHR9 is changed to UCSZ2

• OR is changed to DOR

19.3

Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-

chronous, Master Synchronous and Slave Synchronous mode. The UMSEL bit in USART

Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-

ation. Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA

pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave

mode). The XCK pin is only active when using Synchronous mode.

Figure 19-2 shows a block diagram of the clock generation logic.

ATmega32A Datasheet(PDF) 149 Page - ATMEL Corporation