ATmega32A datasheet(170/352 Pages) ATMEL

170 / 352 page

170

8155B–AVR–07/09

ATmega32A

TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDR.

19.11.4

UCSRC – USART Control and Status Register C

The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing

UBRRH/ UCSRC Registers” on page 165 section which describes how to access this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when

reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between Asynchronous and Synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.

If a mismatch is detected, the PE Flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Bit

765

432

URSEL

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

UCSRC

Read/Write

R/W

Initial Value

Table 19-4.

UMSEL Bit Settings

UMSEL

Mode

Asynchronous Operation

Synchronous Operation

Table 19-5.

UPM Bits Settings

UPM1

UPM0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 19-6.

USBS Bit Settings

USBS

Stop Bit(s)

01-bit

12-bit

ATmega32A Datasheet(PDF) 170 Page - ATMEL Corporation

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