ATmega32A datasheet(171/352 Pages) ATMEL

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8155B–AVR–07/09

ATmega32A

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-

acter Size) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is

used. The UCPOL bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

19.11.5

UBRRL and UBRRH – USART Baud Rate Registers

The UBRRH Register shares the same I/O location as the UCSRC Register. See the “Accessing

UBRRH/ UCSRC Registers” on page 165 section which describes how to access this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when

reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

Table 19-7.

UCSZ Bits Settings

UCSZ2

UCSZ1

UCSZ0

Character Size

5-bit

6-bit

7-bit

8-bit

Reserved

9-bit

Table 19-8.

UCPOL Bit Settings

UCPOL

Transmitted Data Changed (Output of TxD

Pin)

Received Data Sampled (Input on RxD

Pin)

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

Bit

151413

121110

URSEL

–

UBRR[11:8]

UBRRH

UBRR[7:0]

UBRRL

765

432

Read/Write

R/W

Initial Value

000

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