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ATmega32A Datasheet(PDF) 201 Page - ATMEL Corporation

Part # ATmega32A
Description  8-bit Microcontroller with 32K Bytes In-System Programmable Flash
PDF  352 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATmega32A Datasheet(HTML) 201 Page - ATMEL Corporation

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8155B–AVR–07/09
ATmega32A
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same slave. In this
case, neither the slave nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same slave with different data or direction bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are
being addressed by the winning master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure 20-21. Possible status values are given in circles.
Figure 20-21. Possible Status Codes Caused by Arbitration
20.9
Register Description
20.9.1
TWBR – TWI Bit Rate Register
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator
Unit” on page 182 for calculating bit rates.
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLA
START
Data
STOP
Bit
765
432
10
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
TWBR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0



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