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ATmega32A Datasheet(PDF) 203 Page - ATMEL Corporation |
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ATmega32A Datasheet(HTML) 203 Page - ATMEL Corporation |
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203 / 352 page ![]() 203 8155B–AVR–07/09 ATmega32A • Bit 2 – TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. • Bit 1 – Res: Reserved Bit This bit is a reserved bit and will always read as zero. • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti- vated for as long as the TWINT Flag is high. 20.9.3 TWSR – TWI Status Register • Bits 7:3 – TWS: TWI Status These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different sta- tus codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1:0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. To calculate bit rates, see “Bit Rate Generator Unit” on page 182. The value of TWPS1:0 is used in the equation. 20.9.4 TWDR – TWI Data Register Bit 7654 321 0 TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR Read/Write RR RRRR R/W R/W Initial Value 1111 100 0 Table 20-7. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 00 1 01 4 10 16 11 64 Bit 765 432 10 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 |
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