ATmega32A datasheet(280/352 Pages) ATMEL

280 / 352 page

280

8155B–AVR–07/09

ATmega32A

26.9

SPI Serial Programming Pin Mapping

Figure 26-10. SPI Serial Programming and Verify(1)

Notes:

1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V

CC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-

tion. The Chip Erase operation turns the content of every memory location in both the Program

and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

26.9.1

SPI Serial Programming Algorithm

When writing serial data to the ATmega32A, data is clocked on the rising edge of SCK.

When reading data from the ATmega32A, data is clocked on the falling edge of SCK. See Figure

26-11 for timing details.

To program and verify the ATmega32A in the SPI Serial Programming mode, the following

sequence is recommended (See four byte instruction formats in Table 26-14

Table 26-12. Pin Mapping SPI Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB5

Serial Data in

MISO

PB6

Serial Data out

SCK

PB7

Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

PB5

PB6

PB7

+2.7 - 5.5V

AVCC

+2.7 - 5.5V

(2)

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