ATmega32A datasheet(300/352 Pages) ATMEL

300 / 352 page

300

8155B–AVR–07/09

ATmega32A

antees that a Brown-out Reset will occur before VCC drops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 1 and BODLEVEL = 0 for ATmega32A.

27.6

Two-wire Serial Interface Characteristics

Table 27-2 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega32A Two-wire Serial

Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 27-5.

Table 27-2.

Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

Input Low-voltage

-0.5

0.3 V

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

Vhys

(1)

Hysteresis of Schmitt Trigger Inputs

0.05 VCC

(2)

–V

(1)

Output Low-voltage

3 mA sink current

0.4

(1)

Rise Time for both SDA and SCL

20 + 0.1Cb

(3)(2)

300

tof

(1)

Output Fall Time from VIHmin to VILmax

10 pF < Cb < 400 pF

(3)

20 + 0.1Cb

(3)(2)

250

(1)

Spikes Suppressed by Input Filter

50(2)

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

µA

(1)

Capacitance for each I/O Pin

–

SCL

SCL Clock Frequency

(4) > max(16f

SCL, 250kHz)

(5)

400

kHz

Value of Pull-up resistor

fSCL ≤ 100 kHz

fSCL > 100 kHz

HD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

LOW

Low Period of the SCL Clock

SCL ≤ 100 kHz

(6)

4.7

–

µs

fSCL > 100 kHz

(7)

1.3

–

µs

tHIGH

High period of the SCL clock

SCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

SU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

SCL > 100 kHz

0.6

–

µs

HD;DAT

Data hold time

SCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

SCL ≤ 100 kHz

250

–

fSCL > 100 kHz

100

–

VCC 0,4V

–

3mA

----------------------------

1000ns

-------------------

VCC 0,4V

–

3mA

----------------------------

300ns

----------------

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