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ATmega32A Datasheet(PDF) 301 Page - ATMEL Corporation |
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ATmega32A Datasheet(HTML) 301 Page - ATMEL Corporation |
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301 / 352 page  301 8155B–AVR–07/09 ATmega32A Notes: 1. In ATmega32A, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100 kHz. 3. C b = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general f SCL requirement. 6. The actual low period generated by the ATmega32A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7. The actual low period generated by the ATmega32A Two-wire Serial Interface is (1/f SCL - 2/fCK), thus the low time require- ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32A devices connected to the bus may communicate at full speed (400 kHz) with other ATmega32A devices, as well as any other device with a proper tLOW accep- tance margin. Figure 27-5. Two-wire Serial Bus Timing 27.7 SPI Timing Characteristics See Figure 27-6 and Figure 27-7 for details. tSU;STO Setup time for STOP condition f SCL ≤ 100 kHz 4.0 – µs f SCL > 100 kHz 0.6 – µs tBUF Bus free time between a STOP and START condition fSCL ≤ 100 kHz 4.7 – µs f SCL > 100 kHz 1.3 – µs Table 27-2. Two-wire Serial Bus Requirements (Continued) Symbol Parameter Condition Min Max Units tSU;STA tLOW tHIGH tLOW tof tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL SDA tr Table 27-3. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 18-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5Hold Master 10 6 Out to SCK Master 0.5 • t SCK 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs |
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