ATmega644PA datasheet(149/468 Pages) ATMEL

149 / 468 page

149

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform

generated will have a maximum frequency of f

oc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-

ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

16.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 16-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x

and TCNT2.

Figure 16-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

ATmega644PA Datasheet(PDF) 149 Page - ATMEL Corporation