ATmega644PA datasheet(272/468 Pages) ATMEL

272 / 468 page

272

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a

simple digital port pin as described in the section ”I/O-Ports” on page 74. The Boundary-scan

details from Figure 24-3 replaces the dashed box in Figure 24-4.

When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Regis-

ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 24-4 to make the

scan chain read the actual pin value. For analog function, there is a direct connection from the

external pin to the analog circuit. There is no scan chain on the interface between the digital and

the analog circuitry, but some digital control signal to analog circuitry are turned off to avoid driv-

ing contention on the pads.

When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port

pins even if the CKOUT fuse is programmed. Even though the clock is output when the JTAG IR

contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan.

Figure 24-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

Vcc

EXTEST

To Next Cell

ShiftDR

Output Control (OC)

Output Data (OD)

Input Data (ID)

From Last Cell

UpdateDR

ClockDR

FF1

LD1

LD0

FF0

Pull-up Enable (PUE)

ATmega644PA Datasheet(PDF) 272 Page - ATMEL Corporation