ATmega644PA datasheet(337/468 Pages) ATMEL

337 / 468 page

337

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

Notes:

1. In ATmega164PA/324PA/644PA/1284P, this parameter is characterized and not 100% tested.

2. Required only for fSCL > 100 kHz.

3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency

5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices connected to the Two-wire

Serial Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater

than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-

ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32 devices connected to the bus may

communicate at full speed (400 kHz) with other ATmega32 devices, as well as any other device with a proper tLOW accep-

tance margin.

Figure 27-5. 2-wire Serial Bus Timing

tLOW

Low Period of the SCL Clock

SCL ≤ 100 kHz

(6)

4.7

–

µs

SCL > 100 kHz

(7)

1.3

–

µs

tHIGH

High period of the SCL clock

fSCL ≤ 100 kHz

4.0

–

µs

SCL > 100 kHz

0.6

–

µs

SU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hold time

SCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

tSU;DAT

Data setup time

fSCL ≤ 100 kHz

250

–

SCL > 100 kHz

100

–

SU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

condition

SCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

1.3

–

µs

Table 27-12. 2-wire Serial Bus Requirements (Continued)

Symbol

Parameter

Condition

Min

Max

Units

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

tBUF

SCL

SDA

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