74HC595

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2

LOGIC DIAGRAM

SERIAL

DATA

INPUT

14

11

10

12

13

SHIFT

CLOCK

RESET

LATCH

CLOCK

OUTPUT

ENABLE

SHIFT

REGISTER

LATCH

15

1

2

3

4

5

6

7

9

A

GND = PIN 8

PARALLEL

DATA

OUTPUTS

SERIAL

DATA

OUTPUT

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

LATCH CLOCK

OUTPUT ENABLE

A

RESET

SHIFT CLOCK

GND

ORDERING INFORMATION

Device

Package

74HC595DR2G

SOIC−16

(Pb−Free)

2500 Tape & Reel

74HC595DTR2G

TSSOP−16*

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.