BQ20Z60DBT-R1 datasheet(7/15 Pages) TI

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SMBC

SMBD

SMBC

SMBD

SMBC

SMBD

tSU(STA)

tBUF

tSU(STO)

SMBC

SMBD

tTIMEOUT

tHIGH

tLOW

tHD(DAT)

tSU(DAT)

tHD(STA)

Start and Stop condition

Wait and Hold condition

Timeout condition

Repeated Start condition

bq20z60-R1

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SLUS991 – DECEMBER 2009

SMBus TIMING SPECIFICATIONS (continued)

VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tLOW:SEXT Cumulative clock low slave extend time

See (3)

tLOW:MEXT Cumulative clock low master extend time See

(4)

Clock/data fall time

(VILMAX – 0.15 V) to (VIHMIN + 0.15 V)

300

Clock/data rise time

0.9 VCC to (VILMAX – 0.15 V)

1000

(3)

tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4)

tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

SMBus TIMING DIAGRAM

SCLKACK is the acknowledge related clock pulse generated by the master.

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