CS8406-CSZ datasheet(6/42 Pages) CIRRUS

6 / 42 page

DS580F5

CS8406

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Notes:

The active edge of ISCLK is programmable in Software Mode.

The polarity of ILRCK is programmable in Software Mode.

Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.

This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.

Parameter

Symbol

Min

Typ

Max

Units

SDIN Setup Time Before ISCLK Active Edge

(Note 5)

tds

SDIN Hold Time After ISCLK Active Edge

(Note 5)

tdh

Master Mode

OMCK to ISCLK active edge delay

(Note 5)

tsmd

OMCK to ILRCK delay

(Note 6)

tlmd

ISCLK and ILRCK Duty Cycle

Slave Mode

ISCLK Period

tsckw

ISCLK Input Low Width

tsckl

14.4

ISCLK Input High Width

tsckh

14.4

ISCLK Active Edge to ILRCK Edge

(Note 7)

tlrckd

ILRCK Edge Setup Before ISCLK Active Edge

(Note 8)

tlrcks

ISCLK

ILRCK

(output)

OMCK

(input)

smd

lmd

sckh

sckl

sckw

(input)

SDIN

lrcks

lrckd

ISCLK

ILRCK

Figure 1. Audio Port Master Mode Timing

Figure 2. Audio Port Slave Mode and Data Input Timing

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