HT6P20X Series

Rev. 1.60

4

July 30, 2009

S t a n d b y m o d e

T r a n s m i s s i o n

e n a b l e d ?

N o

N o

Y e s

Y e s

P i l o t / A d d r e s s / D a t a / A n t i - c o d e

w o r d s t r a n s m i t t e d

T r a n s m i s s i o n

s t i l l e n a b l e d

P o w e r o n

The HT6P20A/B/D detects the logic state of the internal programmed address and the external data pins, and then trans-

mits the detected information during the code period. Each address/data bit can be set to one of the following two logic

states:

Flowchart

" O n e "

" Z e r o "

f o s c

A d d r e s s /

D a t a b i t