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HT56R66 Datasheet(PDF) 21 Page - Holtek Semiconductor Inc

Part # HT56R66
Description  TinyPower A/D Type with LCD 8-Bit OTP MCU
PDF  104 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT56R66 Datasheet(HTML) 21 Page - Holtek Semiconductor Inc

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HT56R66/HT56R666
Rev. 1.10
21
September 8, 2009
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory. For devices with larger Data Memory ca-
pacities, the General Purpose Data Memory, in addition
to being located in Bank 0, is also stored in Banks 2 to
12, the actual number of banks present depends upon
the device selected.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both read and write type
but some are protected and are read only, the details of
which are located under the relevant Special Function
Register section. Note that for locations that are unused,
any read instruction to these addresses will return the
value
²00H². The Special Function registers are
mapped into all banks and can therefore be accessed
from any bank location.
Display Memory
The data to be displayed on the LCD or LED display is
stored in an area of fully accessible Data Memory. By
writing to this area of RAM, the display output can be di-
rectly controlled by the application program. As this
Memory exists in Bank 1, but have addresses which
map into the General Purpose Data Memory, it is neces-
sary to first ensure that the Bank Pointer is set to the
value 01H before accessing the Display Memory. The
Display Memory can only be accessed indirectly using
the Memory Pointer MP1 and the indirect addressing
register IAR1. When the Bank Pointer is set to Bank 1 to
access the Display Memory, if any addresses with a
value less than 40H are read, the Special Purpose
Memory in Bank 0 will be accessed. Also, if the Bank
Pointer is set to Bank 1, if any addresses higher than the
last address in Bank 1 are read, then a value of 00H will
be returned.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control and
A/D converter operation. The location of these registers
within the Data Memory begins at the address 00H. Any
unused Data Memory locations between these special
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 7 H
3 8 H
3 9 H
3 A H
3 B H
3 C H
3 D H
3 E H
3 F H
H T 5 6 R 6 6
: U n u s e d R e a d a s " 0 0 "
I A R 0
M P 0
I A R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
I N T C 0
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P W M 0 L
P W M 0 H
P W M 1 L
P W M 1 H
I N T C 1
P W M 2 L
P W M 2 H
P W M 3 L
P W M 3 H
A D R L
A D R H
A D C R
A C S R
C L K M O D
P A W U
P A P U
P B P U
P C P U
P D P U
I N T E D G E
L C D C T R L
L C D O U T 1
L C D O U T 2
M I S C
M F I C 0
M F I C 1
S I M C T L 0
S I M C T L 1
S I M D R
S I M A R / S I M C T L 2
T M R 2
T M R 2 C
T M R 3
T M R 3 C
H T 5 6 R 6 6 6
I A R 0
M P 0
I A R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
I N T C 0
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P D
P D C
P W M 0 L
P W M 0 H
P W M 1 L
P W M 1 H
I N T C 1
P W M 2 L
P W M 2 H
P W M 3 L
P W M 3 H
A D R L
A D R H
A D C R
A C S R
C L K M O D
P A W U
P A P U
P B P U
P D P U
I N T E D G E
L E D C T R L
L C D C T R L
L C D O U T 1
L C D O U T 2
M I S C
M F I C 0
M F I C 1
S I M C T L 0
S I M C T L 1
S I M D R
S I M A R / S I M C T L 2
T M R 2
T M R 2 C
T M R 3
T M R 3 C
Special Purpose Data Memory



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