HT68F20 datasheet(139/210 Pages) HOLTEK

139 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev. 1.00

139

November 3, 2009

2C Bus Communication

Communication on the I

2C bus requires four separate

steps, a START signal, a slave device address transmis-

sion, a data transmission and finally a STOP signal.

When a START signal is placed on the I

2C bus, all de-

vices on the bus will receive this signal and be notified of

the imminent arrival of data on the bus. The first seven

bits of the data will be the slave address with the first bit

being the MSB. If the address of the slave device

matches that of the transmitted address, the HAAS bit in

the SIMC1 register will be set and an I

2C interrupt will be

generated. After entering the interrupt service routine,

the slave device must first check the condition of the

HAAS bit to determine whether the interrupt source orig-

inates from an address match or from the completion of

an 8-bit data transfer. During a data transfer, note that

after the 7-bit slave address has been transmitted, the

following bit, which is the 8th bit, is the read/write bit

whose value will be placed in the SRW bit. This bit will

be checked by the slave device to determine whether to

go into transmit or receive mode. Before any transfer of

data to or from the I

2C bus, the microcontroller must in-

itialise the bus, the following are steps to achieve this:

Step 1

Set the SIM2~SIM0 and SIMEN bits in the SIMC0 regis-

ter to

²1² to enable the I2C bus.

Step 2

Write the slave address of the device to the I

2C bus ad-

dress register SIMA.

Step 3

Set the SIME and SIM Muti-Function interrupt enable bit

of the interrupt control register to enable the SIM inter-

rupt and Multi-function interrupt.

2C Bus Start Signal

The START signal can only be generated by the master

device connected to the I

2C bus and not by the slave de-

vice. This START signal will be detected by all devices

connected to the I

2C bus. When detected, this indicates

that the I

2C bus is busy and therefore the HBB bit will be

set. A START condition occurs when a high to low transi-

tion on the SDA line takes place when the SCL line re-

mains high.

Slave Address

The transmission of a START signal by the master will

be detected by all devices on the I

2C bus. To determine

which slave device the master wishes to communicate

with, the address of the slave device will be sent out im-

mediately following the START signal. All slave devices,

after receiving this 7-bit address data, will compare it

with their own 7-bit slave address. If the address sent

out by the master matches the internal address of the

microcontroller slave device, then an internal I

2C bus in-

terrupt signal will be generated. The next bit following

the address, which is the 8th bit, defines the read/write

status and will be saved to the SRW bit of the SIMC1

edge bit, which is a low level, as the 9th bit. The slave

device will also set the status flag HAAS when the ad-

dresses match.

As an I

2C bus interrupt can come from two sources,

when the program enters the interrupt subroutine, the

HAAS bit should be examined to see whether the inter-

rupt source has come from a matching slave address or

from the completion of a data byte transfer. When a

slave address is matched, the device must be placed in

either the transmit mode and then write data to the SIMD

a dummy read from the SIMD register to release the

SCL line.

2C Bus Read/Write Signal

The SRW bit in the SIMC1 register defines whether the

slave device wishes to read data from the I

2C bus or

write data to the I

2C bus. The slave device should exam-

ine this bit to determine if it is to be a transmitter or a re-

ceiver. If the SRW flag is

²1² then this indicates that the

master device wishes to read data from the I

2C bus,

therefore the slave device must be setup to send data to

the I

2C bus as a transmitter. If the SRW flag is

²0² then

this indicates that the master wishes to send data to the

2C bus, therefore the slave device must be setup to

read data from the I

2C bus as a receiver.

2C Bus Slave Address Acknowledge Signal

After the master has transmitted a calling address, any

slave device on the I

2C bus, whose own internal address

matches the calling address, must generate an ac-

knowledge signal. The acknowledge signal will inform

S t a r t

W r i t e S l a v e

A d d r e s s t o S I M A

S E T S I M [ 2 : 0 ] = 1 1 0

S E T S I M E N

I 2 C B u s

I n t e r r u p t = ?

Y e s

N o

S E T S I M E a n d M F n E

W a i t f o r I n t e r r u p t

G o t o M a i n P r o g r a m

C L R S I M E

P o l l S I M F t o d e c i d e

w h e n t o g o t o I 2 C B u s I S R

G o t o M a i n P r o g r a m

2C Bus Initialisation Flow Chart

HT68F20 Datasheet(PDF) 139 Page - Holtek Semiconductor Inc

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