HT68F20 datasheet(142/210 Pages) HOLTEK

142 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev. 1.00

142

November 3, 2009

Peripheral Clock Output

The Peripheral Clock Output allows the device to supply

external hardware with a clock signal synchronised to

the microcontroller clock.

Peripheral Clock Operation

As the peripheral clock output pin, PCK, is shared with

I/O line, the required pin function is chosen via PCKEN

in the SIMC0 register. The Peripheral Clock function is

controlled using the SIMC0 register. The clock source

for the Peripheral Clock Output can originate from either

the TM0 CCRP match frequency/2 or a divided ratio of

the internal fSYS clock. The PCKEN bit in the SIMC0 reg-

ister is the overall on/off control, setting PCKEN bit to

²1² enables the Peripheral Clock, setting PCKEN bit to

²0² disables it. The required division ratio of the system

clock is selected using the PCKP1 and PCKP0 bits in

the same register. If the device enters the SLEEP Mode

this will disable the Peripheral Clock output.

· SIMC0 Register

Bit

76543210

Name

SIM2

SIM1

SIM0

PCKEN

PCKP1

PCKP0

SIMEN

R/W

POR

1110000

Bit 7~5

SIM2, SIM1, SIM0: SIM operating mode control

000: SPI master mode; SPI clock is fSYS/4

001: SPI master mode; SPI clock is fSYS/16

010: SPI master mode; SPI clock is fSYS/64

011: SPI master mode; SPI clock is fTBC

100: SPI master mode; SPI clock is TM0 CCRP match frequency/2

101: SPI slave mode

110: I

2C slave mode

111: Unused mode

These bits setup the overall operating mode of the SIM function. As well as selecting if the I

or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock

frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced

from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external

Master device.

Bit 4

PCKEN: PCK output pin control

0: Disable

1: Enable

Bit 3~2

PCKP1, PCKP0: select PCK output pin frequency

00: fSYS

01: fSYS/4

10: fSYS/8

11: TM0 CCRP match frequency/2

Bit 1

SIMEN: SIM control

0: Disable

1: Enable

The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero

to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a

floating condition and the SIM operating current will be reduced to a minimum value. When the bit

is high the SIM interface is enabled. The SIM configuration option must have first enabled the

SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high

the contents of the SPI control registers will be in an unknown condition and should therefore be

first initialised by the application program.

Bit 0

unimplemented, read as

²0²

HT68F20 Datasheet(PDF) 142 Page - Holtek Semiconductor Inc

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