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HT82V38 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc |
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HT82V38 Datasheet(HTML) 4 Page - Holtek Semiconductor Inc |
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4 / 16 page  Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions Analog Inputs RFS Full-scale Input Range ¾¾ ¾ 1.6/2.0 ¾ V Vi Input Limits ¾¾ AVSS-0.3 ¾ AVDD+0.3 V Ci Input Capacitance ¾¾ ¾ 10 ¾ pF Ii Input Current ¾¾ ¾ 10 ¾mA Amplifiers PGA Gain at Minimum ¾¾ ¾ 1 ¾ V/V PGA Gain at Maximum ¾¾ ¾ 5.85 ¾ V/V PGA Gain Resolution ¾¾ ¾ 6 ¾ Bits Programmable Offset at Minimum ¾¾ ¾ -250 ¾ mV Programmable Offset at Maximum ¾¾ ¾ 250 ¾ mV Offset Resolution ¾¾ ¾ 9 ¾ Bits Clamp DAC Circuit tA Clamp DAC resolution ¾¾ ¾ 4 ¾ Bits Clamp DAC output voltage at code 0 ¾ 0.45 ¾ V Clamp DAC output voltage at code F ¾ 2.7 ¾ V Clamp DAC Step size ¾ 0.15 ¾ V/Step Clamp DAC deviation (AVDD=3.300V) -50 ¾ 50 mV Temperature Range tA Operating ¾¾ 0 ¾ 70 °C Power Consumption Ptot Total Power Consumption ¾¾ ¾ 300 ¾ mW Timing Specification AVDD=DRVDD=3.3V, AVSS=DRVSS=0V, Ta=25 °C, ADCCLK=30MHz unless otherwise stated Symbol Parameter Min. Typ. Max. Unit Clock Parameters tPRA 3-Channel Pixel Rate 100 ¾¾ ns tPRB 2-Channel Pixel Rate 66 ¾¾ ns tPRC 1-Channel Pixel Rate 50 ¾¾ ns tADCLK ADCCLK Pulse Width 16 ¾¾ ns tC1 CDSCLK1 Pulse Width 10 ¾¾ ns tC2 CDSCLK2 Pulse Width 10 ¾¾ ns tC1C2 CDSCLK1 Falling to CDSCLK2 Rising 0 ¾¾ ns tADC2 ADCCLK Falling to CDSCLK2 Rising 2 ¾¾ ns tC2ADR CDSCLK2 Rising to ADCCLK Rising 2 ¾¾ ns tC2ADF CDSCLK2 Falling to ADCCLK Falling 20 ¾¾ ns tADC1 ADCCLK Falling to CDSCLK1 Rising 0 ¾¾ ns tAD Aperture Delay for CDS Clocks ¾ 3 ¾ ns HT82V38 Rev. 1.00 4 July 23, 2009 |
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