eorex

Preliminary

EM48AM1684VBD

Mar. 2008

www.eorex.com

256Mb (4M

Features

• Fully Synchronous to Positive Clock Edge

• Single 2.7V ~ 3.6V Power Supply

• LVTTL Compatible with Multiplexed Address

• Programmable Burst Length (B/L) - 1, 2, 4, 8

or Full Page

• Programmable CAS Latency (C/L) - 2 or 3

• Data Mask (DQM) for Read / Write Masking

• Programmable Wrap Sequence

– Sequential (B/L = 1/2/4/8/full Page)

– Interleave (B/L = 1/2/4/8)

• Burst Read with Single-bit Write Operation

• All Inputs are Sampled at the Rising Edge of

the System Clock

• Auto Refresh and Self Refresh

• 8,192 Refresh Cycles / 64ms (7.8us)

Description

The EM48AM1684VBD is Synchronous Dynamic

Random Access Memory (SDRAM) organized as

4Meg words x 4 banks by 16 bits. All inputs and

outputs are synchronized with the positive edge of

the clock.

The 256Mb SDRAM uses synchronized pipelined

architecture to achieve high speed data transfer

rates and is designed to operate at 3.3V low power

memory system. It also provides auto refresh with

power saving / down mode. All inputs and outputs

voltage levels are compatible with LVTTL.

Available packages:TFBGA 54B 12mm x 8mm.

Ordering Information

Part No

Organization

Max. Freq

Package

Grade

Pb

EM48AM1684VBD-75F

16M X 16

133MHz @CL3

TFBGA -54B

Commercial

Free

EM48AM1684VBD-75FE

16M X 16

133MHz @CL3

TFBGA -54B

Extend temp.

Free

* EOREX reserves the right to change products or specification without notice.

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