ST7556

Ver 2.2

17/43

2005/10/05

DISPLAY DATA RAM (DDRAM)

The ST7556 contains a 65X102 bit static RAM that stores the display data. The display data RAM store the dot data for the

LCD. It has a 65(8 pageX8 +1) X102, and extra ICOM. There is a direct correspondence between X-address and column

output number. It is 65-row by 102-column addressable array. Each pixel can be selected when the page and column

addresses are specified. The 65 rows are divided into 8 pages of 8 lines and 1 page of 1 line. Data is read from or written to

the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the

LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller

operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD

flicker.

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 6. It incorporates 4-bit Page

Address register changed by only the “Set Page” instruction. Page Address 9 is a special RAM area for the icons and

display data D0 is only valid.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in

figure 5. The display data RAM column address is specified by the Column Address Set command. The specified column

address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed

continuously.

ADDRESSING

Data is downloaded in bytes into the RAM matrix of ST7556 as indicated in Figs.5, 6, 7. The display RAM has a matrix of

65 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 8 (1000).

Addresses outside these ranges are not allowed.

In vertical addressing mode (V=1) the Y address increments after each byte (see Fig.7). After the last Y address (Y = 8) Y

wraps around to 0 and X increments to address the next column.

In horizontal addressing mode (V=0) the X address increments after each byte (see Fig.6). After the last X address

(X = 101) X wraps around to 0 and Y increments to address the next row.

After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0)

N

Dummy

D(N)

D(N+1)

MPU signal

A0

/W R

D0 to D7

Internal signals

/W R

COLUMN ADDRESS

/RD

N

D(N)

D(N+1) D(N+2)

D(N)

D(N+1) D(N+2)

N

/RD

BUS HOLDER

Fig 4. Read Timing