74LVC_LVCH1T45_2

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 02 — 19 January 2010

23 of 30

NXP Semiconductors

74LVC1T45; 74LVCH1T45

Dual supply translating transceiver; 3-state

14.2 Bidirectional logic level-shifting application

Figure 16 shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic

level-shifting application. Since the device does not have an output enable pin, the system

designer should take precautions to avoid bus contention between system-1 and

system-2 when changing directions.

Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2

and then from system-2 to system-1.

[1]

H = HIGH voltage level;

L = LOW voltage level;

Z = high-impedance OFF-state.

Pull-up or pull-down only needed for 74LVC1T45.

Fig 16. Bidirectional logic level-shifting application

Table 17.

Description bidirectional logic level-shifting application[1]

State

DIR CTRL I/O-1

I/O-2

Description

1

H

output

input

system-1 data to system-2

2

H

Z

Z

system-2 is getting ready to send data to system-1.

I/O-1 and I/O-2 are disabled. The bus-line state

depends on bus hold.

3

L

Z

Z

DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.

The bus-line state depends on bus hold.

4

L

input

output

system-2 data to system-1

001aaj995

74LVC1T45

74LVCH1T45

1

2

3

GND

system-1

system-2

A

6

5

4

DIR

B

I/O-1

I/O-2

PULL-UP/DOWN

DIR CTRL

PULL-UP/DOWN