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AS1747 Datasheet(PDF) 9 Page - ams AG |
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AS1747 Datasheet(HTML) 9 Page - ams AG |
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9 / 13 page ![]() www.austriamicrosystems.com Revision 1.01 9 - 13 AS1747 Datasheet - Ti m i n g D i a g r a m s 10 Timing Diagrams Figure 15. Switching Time Figure 16. Break-Before-Make Interval Figure 17. Charge Injection VOUT CL RL VN_ VCC VCC COM_ IN_ NO_ OR NC_ GND Logic Input CL includes fixture and stray capacitance VOUT = VN_(RL / (RL + RON)) 50% tr < 5ns tf < 5ns 0V 0V VOUT tON tOFF 0.9 x VOUT 0.9 x VOUT Logic Input Switch Output VCC IN depends on switch configuration; Input polarity determined by sense of switch. VOUT CL RL VN_ VCC VCC COM_ IN_ NO_ GND Logic Input CL includes fixture and stray capacitance 50% 0V VOUT tBBM 0.9 x VOUT Logic Input VCC NC_ VOUT CL VCC VCC COM_ NC_ OR NO_ Logic input waveforms inverted for switches that have the opposite logic sense. GND VIL to VIH RGEN VGEN + IN_ ΔVOUT VOUT Q = ( ΔVOUT)(CL) ON ON OFF OFF OFF OFF IN IN |
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