US1010

2-5

Rev. 1.3

10/30/00

Thermal Design

The US1010 incorporates an internal thermal shutdown

that protects the device when the junction temperature

exceeds the maximum allowable junction temperature.

Although this device can operate with junction tempera-

tures in the range of 150

selected heat sink be chosen such that during maxi-

mum continuous load operation the junction tempera-

ture is kept below this number. The example below for

a SCSI terminator application shows the steps in se-

lecting the proper regulator in a surface mount pack-

age .(See US1015 for non surface mount packages)

Assuming the following specifications :

as shown in figure 4.

The steps for selecting the right package with proper

board area for heatsinking to keep the junction tem-

perature below 135

1) Calculate the maximum power dissipation using :

2) Calculate the maximum

ample:

2) Select a package from the datasheet with lower

than the one calculated in the previous step.

Selecting TO252 (D Pak) with at least 0.5" square of

0.062" FR4 board using 1OZ copper has 70

which is lower than the calculated number.

(

)

(

)

P

I

V

V

P

W

D

OUT

IN

OUT

D

=

×

−

−

=

×

−

−

=

0 8

5

0 5

2 85

132

.

.

.

.

θ

θ

JA

J

A

D

JA

MAX

MAX

T

T

P

C W

=

−

=

−

=

°

135

35

132

75 6

.

.

/

To set the output DC voltage, we need to select R1 and

R2 :

3) Assuming R1=121

Select R2=154

Ω

V

V

V

V

V

V

I

A

T

C

IN

F

O

OUT

A

MAX

=

=

=

=

=

°

5

0 5

2 85

0 8

35

.

.

.

R

V

V

OUT

REF

2

1

121

2 85

125

1

121

=

−









×

=

−









×

=

.

.

154.8

Ω

Figure 4 - Final Schematic for half of the

GTL+ termination regulator.

2.85V

1010app4-1.3

R1

121

1%

R2

154

1%

5V

C2

22uF

C1

10uF

US1010

Adj

Vout

Vin

D1

Layout Consideration

The output capacitors must be located as close to

the Vout terminal of the device as possible. It is recom-

mended to use a section of a layer of the PC board as a

plane to connect the Vout pin to the output capacitors to

prevent any high frequency oscillation that may result

due to excessive trace inductance.