HT7612 datasheet(8/18 Pages) HOLTEK

8 / 18 page

HT7612

Rev. 1.20

February 9, 2010

LVD & CDS Detecting Circuit

The external and internal detecting circuits for LVD and

CDS are shown as Fig.13. When the input voltage VLVD

is lower than VH, the comparator outputs low level and it

means that the VDD is lower than minimum operating

voltage (Vmin). When the VCDS is lower than VL, the

comparator outputs high level and it means that it is day-

time, otherwise it is night.

Where

B U Z / L V D

B U Z / C D S

T E S T / S C

R X

R L V D

V D D

R C D S

R Y

V R E F

Fig.13 External Application Circuit

Note:

When the CDS input voltage is lower than VL,it

means that a daytime condition exists for the

PIR circuit.

The Criterion of LVD and CDS

The LVD and CDS trigger timing are shown as Fig.14 and Fig.15 respectively. In Fig.14, When the LVD condition oc-

curs, the LED will be flicker and the buzzer will emit such as a tone. In Fig.15, When the CDS is changed from high to

low, the output of PIR is high after 10sec, and when the CDS is changed from low to high, the output of PIR is low at the

moment.

Fig.14 Trigger Timing of LVD

Fig.15 Trigger Timing of CDS

D D

L V D

R E F

C D S

HT7612 Datasheet(PDF) 8 Page - Holtek Semiconductor Inc